Intellectual Property India Publishes Patent Application for An Fpga-Based Event-Driven Multiplier-Less Fir Filter For Low-Power Speech Processing

MUMBAI, India, Nov. 13 -- Intellectual Property India has published a patent application (202641123509 A) filed by K. S. Rangasamy College Of Technology on October 15, 2026, for An Fpga-Based Event-Driven Multiplier-Less Fir Filter For Low-Power Speech Processing.

Inventors include Mr. D. Poornakumar; Dr. P. Kumar; Mr. D. Dhanasekaran; Mr. S. Jeyaprakasam; Ms. S. Dharanisri; Ms. M. Shanmugapriya; Mr. V. Moulishwaran; and Mr. P. Muthu Adithya.

The application for the patent was published on November 13, 2026, under issue no. 46/2026.

Abstract: The proposed system presents a combined FPGA architecture for speech filtering by integrating an event-driven activity-control section with a multiplier-less Distributed Arithmetic finite impulse re...