Intellectual Property India Publishes Patent Application for An Apparatus For Accelerating Reductionist Matrix Operations With Guaranteed Linear Memory Traffic

MUMBAI, India, July 13 -- Intellectual Property India has published a patent application (202611043901 A) filed by Indian Institute Of Technology, Jammu on April 06, 2026, for An Apparatus For Accelerating Reductionist Matrix Operations With Guaranteed Linear Memory Traffic.

Inventors include Singh, Dashpreet; Meena, Anil; and Ranjan, Uma Satya.

The application for the patent was published on July 10, 2026, under issue no. 28/2026.

Abstract: Embodiments of the present disclosure relate to an apparatus (100) for accelerating matrix multiplication operations resulting in data of reduced dimensionality. The apparatus (100) includes a hardware-based stream fetcher (102) that retrieves input tensors from an off-chip memory (104) into on-chip ...