Intellectual Property India Publishes Patent Application for A System And Method For Leakage Current Reduction Using Current Mode Logic Circuits

MUMBAI, India, June 30 -- Intellectual Property India has published a patent application (202641074414 A) filed by Cvr College Of Engineering on June 16, 2026, for A System And Method For Leakage Current Reduction Using Current Mode Logic Circuits.

Inventors include Dr K. A. Jyotsna; and Gera Vijaya Nirmala.

The application for the patent was published on June 26, 2026, under issue no. 26/2026.

Abstract: The current invention offers a way to reduce circuit leakage current utilizing current mode logic, as well as a system to do so. An object of the invention is to reduce leakage current in sub-threshold circuits and to operate transistors in weak inversion region for ultra-low power operation thereby improving power-delay product which re...