Intellectual Property India Publishes Patent Application for A Hybrid Low-Power Architecture For A Binary Coded Decimal (bcd) Adder

MUMBAI, India, July 7 -- Intellectual Property India has published a patent application (202641078561 A) filed by Sr University on June 25, 2026, for A Hybrid Low-Power Architecture For A Binary Coded Decimal (bcd) Adder.

Inventors include Dr. Ts. Narayanamurthy; Dr. Ch. Rajendra Prasad; and Dr. Roseline Oluwaseun Ogundokun.

The application for the patent was published on July 03, 2026, under issue no. 27/2026.

Abstract: A HYBRID LOW-POWER ARCHITECTURE FOR A BINARY CODED DECIMAL (BCD) ADDER The present invention relates to a hybrid low-power architecture for Binary Coded Decimal (BCD) adders that integrates power gating, clock gating, and multi- VDD techniques under a unified control framework. The architecture comprises control logic, a...