MUMBAI, India, April 17 -- Intellectual Property India has published a patent application (202641043577 A) filed by Vellore Institute Of Technology, Vellore, Tamil Nadu, on April 6, for 'system for assertion-level verification of handwritten mathematical proofs using logic conversion.'
Inventor(s) include Sujatha R; Dheeraj Sutram; Tanmay Aaglave; and Akshat Pandey.
The application for the patent was published on April 17, under issue no. 16/2026.
According to the abstract released by the Intellectual Property India: "System for Assertion-Level Verification of Handwritten Mathematical Proofs Using Logic Conversion. The present invention discloses a system for assertion-level verification of handwritten mathematical proofs by integrating ...