Intellectual Property India Publishes Patent Application for 'Real Time Eeg Artifact Suppression Vlsi Asic With Adaptive Blind Source Separation - Hardware Chip That Cleans Eeg Signals On The Fly' Filed by Pace Institute Of Technology And Sciences

MUMBAI, India, Feb. 6 -- Intellectual Property India has published a patent application (202541126582 A) filed by Pace Institute Of Technology And Sciences, Vijayawada, Andhra Pradesh, on Dec. 14, 2025, for 'real time eeg artifact suppression vlsi asic with adaptive blind source separation - hardware chip that cleans eeg signals on the fly..'

Inventor(s) include S. Ch. Kantharao; B. Vijaya; Dr M Apparao; G. Vijay Kiran; and Dr. Vijayachandra Kavuri.

The application for the patent was published on Feb. 6, under issue no. 06/2026.

According to the abstract released by the Intellectual Property India: "The invention discloses a Very Large Scale Integration (VLSI) Application-Specific Integrated Circuit (ASIC) for real-time suppression of ar...