Intellectual Property India Publishes Patent Application for 'Low Power High-Speed Area Efficient Adder Using Quantum Dot Cellular Automata-A Nano Technology Method' Filed by R. M. K. College Of Engineering And Technology

MUMBAI, India, Jan. 9 -- Intellectual Property India has published a patent application (202541044873 A) filed by R. M. K. College Of Engineering And Technology, Chennai, Tamil Nadu, on May 9, 2025, for 'low power high-speed area efficient adder using quantum dot cellular automata-a nano technology method.'

Inventor(s) include Ms. P. Sivalakshmi; and Dr. K. Sangeethalakshmi.

The application for the patent was published on Jan. 9, under issue no. 02/2026.

According to the abstract released by the Intellectual Property India: "The main concerns with VLSI circuit design are power, area, and complexity. This work uses Quantum Dot Cellular Automata (QCA) to design and implement a fast adder. Compared to other designs, the QCA design uses fewe...