Intellectual Property India Publishes Patent Application for 'Fpga Implementation Of Multipliers Using Reversible Logic Gates' Filed by Srinivasa Ramanujan Institute Of Technology; Mr. Y. Madhusudhana; T. Pallavi; Y. Bhavya; and V. Karthikeya

MUMBAI, India, May 1 -- Intellectual Property India has published a patent application (202641049571 A) filed by Srinivasa Ramanujan Institute Of Technology; Mr. Y. Madhusudhana; T. Pallavi; Y. Bhavya; and V. Karthikeya, Ananthapuramu, Andhra Pradesh, on April 18, for 'fpga implementation of multipliers using reversible logic gates.'

Inventor(s) include Srinivasa Ramanujan Institute Technology; Mr. Y. Madhusudhana; T. Pallavi; Y. Bhavya; and V. Karthikeya.

The application for the patent was published on May 1, under issue no. 18/2026.

According to the abstract released by the Intellectual Property India: "Power dissipation and delay are major challenges in modern VLSI systems, particularly in arithmetic units used for Digital Signal Proc...