Intellectual Property India Publishes Patent Application for 'Design Of Low-Power 8-Bit Multiplier Using Approximate Adders For Error Tolerant Applications' Filed by Seshadri Rao Gudlavalleru Engineering College; Mrs. T. Venkata Lakshmi; Chebrolu Sriharsha; and Devanaboyina Anusha

MUMBAI, India, May 1 -- Intellectual Property India has published a patent application (202641048371 A) filed by Seshadri Rao Gudlavalleru Engineering College; Mrs. T. Venkata Lakshmi; Chebrolu Sriharsha; and Devanaboyina Anusha, Gudlavalleru, Andhra Pradesh, on April 16, for 'design of low-power 8-bit multiplier using approximate adders for error tolerant applications.'

Inventor(s) include Seshadri Rao Gudlavalleru Engineering College; Mrs. T. Venkata Lakshmi; Chebrolu Sriharsha; and Devanaboyina Anusha.

The application for the patent was published on May 1, under issue no. 18/2026.

According to the abstract released by the Intellectual Property India: "Binary multiplication is a key arithmetic operation in digital systems, but conventi...