Intellectual Property India Publishes Patent Application for 'Design and Analysis of PLL Components in 45 nm CMOS: Optimized PFD, CP, VCO, and Dividers' Filed by P A Nageswara Rao; M Harshith Mouli; Gurugubelli Manisha; Terukuti Tulasi Ram; Ati Venkata Sudhindra Kumar; and Venkatesh Seerapu

MUMBAI, India, May 1 -- Intellectual Property India has published a patent application (202641048603 A) filed by P A Nageswara Rao; M Harshith Mouli; Gurugubelli Manisha; Terukuti Tulasi Ram; Ati Venkata Sudhindra Kumar; and Venkatesh Seerapu, Visakhapatnam, Andhra Pradesh, on April 16, for 'design and analysis of pll components in 45 nm cmos: optimized pfd, cp, vco, and dividers.'

Inventor(s) include P A Nageswara Rao; M Harshith Mouli; Gurugubelli Manisha; Terukuti Tulasi Ram; Ati Venkata Sudhindra Kumar; and Venkatesh Seerapu.

The application for the patent was published on May 1, under issue no. 18/2026.

According to the abstract released by the Intellectual Property India: "Design and analysis of Phase-Locked Loop (PLL) components i...