Intellectual Property India Publishes Patent Application for 'A Scalable Multi-Processor System-On-Chip With Adaptive Inter-Core Communication Architecture' Filed by Dr. Isaivani Mariyappan; Suresh Kannan S; Anuja K S; and Saranya V

MUMBAI, India, Feb. 27 -- Intellectual Property India has published a patent application (202541131908 A) filed by Dr. Isaivani Mariyappan; Suresh Kannan S; Anuja K S; and Saranya V, Madurai, Tamil Nadu, on Dec. 26, 2025, for 'a scalable multi-processor system-on-chip with adaptive inter-core communication architecture.'

Inventor(s) include Dr. Isaivani Mariyappan; Suresh Kannan S; Anuja K S; and Saranya V.

The application for the patent was published on Feb. 27, under issue no. 09/2026.

According to the abstract released by the Intellectual Property India: "A scalable multi-processor system-on-chip (MPSoC) with an adaptive inter-core communication architecture is disclosed. The system integrates a plurality of processing cores on a sing...