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US Patent Issued to Changxin Memory Technologies on Sept. 8 for "Method for determining performance of sequential logic elements and device" (Chinese Inventor)

ALEXANDRIA, Va., Sept. 8 -- United States Patent no. 12,730,952, issued on Sept. 8, was assigned to Changxin Memory Technologies Inc. (Hefei, China). "Method for determining performance of sequential... Read More


US Patent Issued to The Math Works on Sept. 8 for "Systems and methods for deploying frame-based simulation models on programmable logic devices" (Massachusetts Inventors)

ALEXANDRIA, Va., Sept. 8 -- United States Patent no. 12,730,953, issued on Sept. 8, was assigned to The Math Works Inc. (Natick, Mass.). "Systems and methods for deploying frame-based simulation mode... Read More


US Patent Issued to Synopsys on Sept. 8 for "Statistical timing characterization of superconducting electronic circuit designs" (Colorado Inventor)

ALEXANDRIA, Va., Sept. 8 -- United States Patent no. 12,730,954, issued on Sept. 8, was assigned to Synopsys Inc. (Sunnyvale, Calif.). "Statistical timing characterization of superconducting electron... Read More


US Patent Issued to TEXAS INSTRUMENTS on Sept. 8 for ""Weak" undriven state modelling for power management verification" (Indian Inventors)

ALEXANDRIA, Va., Sept. 8 -- United States Patent no. 12,730,955, issued on Sept. 8, was assigned to TEXAS INSTRUMENTS Inc. (Dallas). ""Weak" undriven state modelling for power management verification... Read More


US Patent Issued to Cornami on Sept. 8 for "Method and system for providing fault tolerant layout of massively parallel processing array" (Texas Inventors)

ALEXANDRIA, Va., Sept. 8 -- United States Patent no. 12,730,956, issued on Sept. 8, was assigned to Cornami Inc (Campbell, Calif.). "Method and system for providing fault tolerant layout of massively... Read More


US Patent Issued to Cadence Design Systems on Sept. 8 for "Route-based cell merging" (British, American Inventors)

ALEXANDRIA, Va., Sept. 8 -- United States Patent no. 12,730,957, issued on Sept. 8, was assigned to Cadence Design Systems Inc. (San Jose, Calif.). "Route-based cell merging" was invented by Edward B... Read More


US Patent Issued to Cadence Design Systems on Sept. 8 for "Non-critical child node-based insertion delay optimization in circuit design" (American, Brazilian Inventors)

ALEXANDRIA, Va., Sept. 8 -- United States Patent no. 12,730,958, issued on Sept. 8, was assigned to Cadence Design Systems Inc. (San Jose, Calif.). "Non-critical child node-based insertion delay opti... Read More


US Patent Issued to D2S on Sept. 8 for "Using a machine-trained network to perform physical design" (California Inventors)

ALEXANDRIA, Va., Sept. 8 -- United States Patent no. 12,730,959, issued on Sept. 8, was assigned to D2S INC. (San Jose, Calif.). "Using a machine-trained network to perform physical design" was inven... Read More


US Patent Issued to TAIWAN SEMICONDUCTOR MANUFACTURING on Sept. 8 for "Devices with track-based fill (TBF) metal patterning" (Taiwanese Inventors)

ALEXANDRIA, Va., Sept. 8 -- United States Patent no. 12,730,960, issued on Sept. 8, was assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. (Hsinchu, Taiwan). "Devices with track-based fill (... Read More


US Patent Issued to Adobe on Sept. 8 for "Generating typographic decorations" (Indian Inventors)

ALEXANDRIA, Va., Sept. 8 -- United States Patent no. 12,730,961, issued on Sept. 8, was assigned to Adobe Inc. (San Jose, Calif.). "Generating typographic decorations" was invented by Arushi Jain (De... Read More